The Digital Autonomy with RISC-V in Europe, Special Grant Agreement 1 (DARE SGA1) project officially launches the first phase of an important initiative. The aim is to develop next-generation European processors and computing systems. This includes an optimized software ecosystem designed for applications in research and industry.
Supported by EuroHPC, a joint venture of the European Union, and coordinated by the Barcelona Supercomputing Center (BSC-CNS), DARE SGA1 brings together 38 leading partners from across Europe. The joint venture is supported by the European Union's Horizon Europe research and innovation program. Germany, Spain, the Czech Republic, Italy, the Netherlands, Belgium, Finland, Greece, Croatia, Portugal, Poland, Sweden, France and Austria are also involved.
Full control over critical computing infrastructure
With a budget of 240 million euros for the first phase, this three-year project forms part of the six-year DARE initiative. DARE SGA1 aims to build a complete European supercomputing hardware (HW) and software (SW) stack for HPC and AI, including high-performance and energy-efficient processors designed and developed in Europe. The initiative is a direct response to Europe's strategic need for digital sovereignty. The continent should have full control over its critical computing infrastructure. Every company, not just the big players, needs access to the computing power it needs. AI developers should compete based on their innovative strength, not just their access to chips or the size of their financial power.
Building the software stack as the overarching project goal
The kick-off event on March 10 and 11, 2025 at the Barcelona Supercomputing Center highlighted the overarching project goal: to build the software stack required for a commercially viable Made-in-Europe HPC chip industry and the procurement of future EU supercomputers with these chips. The TUM School of CIT will play a key role in this: Under the leadership of Carsten Trinitis (Chair of Computer Architecture and Operating Systems in Heilbronn) and Martin Schulz (Chair of Computer Architecture and Parallel Systems in Garching), the open source debugger gdb will be adapted to the instruction extensions for RISC-V developed in the project and integrated into the parallel HPC infrastructure. “This is an important step towards European HPC systems and we are delighted to be involved,” explain the two professors.